1. Field of the Invention
The invention relates generally to digital encode and decode circuitry and, more particularly, but not by way of limitation, it relates to improvements in circuitry for serial storage of digital code for subsequent comparison in multiple parts to increase the speed within which a code can be verified. For example, the invention is utilized in a system for sychronizing the start signal to independent sweep generators of a seismic acquisition system.
2. Description of the Prior Art
The prior art includes a number of different encoder-decoder systems that are commercially available for use in the related seismic field. Such prior systems may incorporate a pseudo random code, phase shift tones, frequency shift tones, on-off tone signals and other sychronizing means, all of which prior systems have various degrees of reliability and timing accuracy. Some require lengthy transmissions over an associated communication link, and this type of system has poor accuracy and reliability in low signal-two-noise conditions.
Prior art of interest is U.S. Pat. No. 3,739,870 in the name of Pelton et al that teaches one form of prior art system that requires extended transmission over a communications link in order to establish a code verification. This system utilizes a pseudo random code of 128 code bits with 0.9765 milliseconds bit duration thereby establishing a total code length of 125 ms. The decoder then samples the code at a 245.09 .mu.s rate to give four samples per bit with 512 bits in shift register storage. Data shift and comparison is then carried out at a 2.097 megahertz rate with a maximum timing error of 245 .mu.s. Such timing accuracy is not acceptable for use with vibrator sources that use higher transmission frequencies in the seismic band because the starting phase of the various sweep generators is too great with the 245 .mu.s timing accuracy. Thus, in pursuing the same method, an increase of 4-to-1 in accuracy would require clocking frequencies of 16-to-1 or 33.574 megahertz. Speeds applicable in the 33 megahertz range would require multilayer printed circuit boards, special techniques, special logic chips and other compromises that are impractical. Accordingly, the present invention strives to reduce such starting phase difference without such penalties.